1. Technical Field
This invention relates generally to a multiple-node system having a number of nodes communicatively connected to an interconnect, and more particularly to the connection paths between each node and the interconnect.
2. Description of the Prior Art
There are many different types of multi-processor computer systems. A Symmetric Multi-Processor (SMP) system includes a number of processors that share a common memory. SMP systems provide scalability. As needs dictate, additional processors can be added. SMP systems usually range from two to 32 or more processors. One processor generally boots the system and loads the SMP operating system, which brings the other processors online. Without partitioning, there is only one instance of the operating system. The operating system uses the processors as a pool of processing resources, all executing simultaneously, where each processor either processes data or is in an idle loop waiting to perform a task. SMP systems increase in speed whenever processes can be overlapped.
A Massively Parallel Processor (MPP) system can use thousands or more processors. MPP systems use a different programming paradigm than the more common SMP systems. In an MPP system, each processor contains its own memory and a copy of the operating system and application, or a portion of the application. Each subsystem communicates with the others through a high-speed interconnect. To use an MPP system effectively, an information-processing problem should be breakable into pieces that can be solved simultaneously. For example, in scientific environments, certain simulations and mathematical problems can be split apart and each part processed at the same time.
A Non-Uniform Memory Access (NUMA) system is a multi-processing system in which memory is separated into distinct banks. NUMA systems are types of SMP systems. In SMP systems, however, all processors access a common memory at the same speed. By comparison, in a NUMA system, memory on the same processor board, or in the same building block or node, as the processor is accessed faster than memory on other processor boards, or in other building blocks or nodes. That is, local memory is accessed faster than distant shared memory. NUMA systems generally scale better to higher numbers of processors than SMP systems.
Multiple-node systems in general have the nodes communicatively connected to one another through an interconnect. The interconnect may be one or more routers, one or more switches, one or more hubs, and so on. The transaction managers of each node in particular are communicatively connected to the interconnect, so that they can communicate with the other nodes. If a fault develops in the path of one of the transaction managers and the interconnect, this means that the transaction manager in question will not be able to communicate with the other nodes to ensure that memory and input/output (I/O) requests are serviced by the appropriate resources. In a NUMA system, this means that the transaction manager will not be able to access the remote resources of the other nodes. The transaction manager may thus not be able to operate properly when it does not have such remote resource access. For this and other reasons, therefore, there is a need for the present invention.